Mobile devices such as mobile phones, mobile internet devices (MIDs) and laptops, are designed with smaller form factor and slimmer profile for improved aesthetic and functional appeals. The size of and real estate occupied by semiconductor packages in the devices need to be scaled down accordingly. Package-on-package (PoP) packaging technology is employed to stack a semiconductor package on top of another semiconductor package to remove the x and y dimensions constraints in the layout of semiconductor packages on a motherboard.
PoP technology presents various problems, particularly with respect to the original equipment manufacturer (OEM) process. One of the problems is the limitation of cold surface to cold surface solder reflow process. FIG. 1 is a cross-sectional view of a known package-on-package (PoP) assembly. Bottom device package 150 may be a core chip such as a microprocessor unit and includes die 170, substrate 160, inter-package contact pads 155 on the top side of bottom package 150, micro balls 180 attached to inter-package contact pads 155, and second level interconnect pads 190 attachable to a motherboard (not shown). Top device package 100 is stacked onto bottom package 150 to form an electrical connection therebetween. Top device package 100 may be a peripheral chip such as a memory or cache unit, and may include die 120 interconnected to substrate 110 via wire bond 130 and encapsulated by molding 125. The bottom side of top device package 100 includes micro balls 140 reflowed and electrically connected to micro balls 180 on the top side of bottom device package 150. During the OEM process, accurate placement and reflow of top device package 100 on bottom device package 150 are typically limited and difficult to control due to the curved surfaces of micro balls 140, 180 and result in poor stacking yield. Further, the pitch of micro balls 140 of top device package 100 is limited by the pitch of micro balls 180 of bottom device package 150. A change in the ball pitch of top device package 100 necessitates a change in the ball pitch of the bottom device package 150 and vice versa.
Another problem typically associated with PoP packaging is the coefficient of thermal expansion (CTE) mismatch between top device package 100 and bottom device package 150. The CTE mismatch is due to the fact that top device package 100 and bottom device package 150 are made from different materials and undergo different rates of thermal expansion in an elevated temperature range. The different rates of expansion and contraction result in warpage of the PoP assembly. Warpage of the PoP assembly presents process challenges in the package stacking process step and quality of joint formation between top device package 100 and bottom device package 150. Intrinsic stresses accumulated in the solder joints between the packages may risk quality and reliability failures during the use of the device.